VGA background Information

VGA is a legacy computer graphics standard introduced by IBM in 1987. It supports various resolutions and color formats and is widely recognized by its iconic 15-pin D-sub connector. Common VGA resolutions go up to 1920x1200 (WUXGA) with a 24-bit color depth.

VGA Controller Design Basics

To create a basic VGA controller, five key signals must be considered: the analog color channels (R, G, B) and the synchronization signals (hsync and vsync). These signals are present on the physical VGA connector and play distinct roles:

Analog Color Signals (R, G, B):

These signals convey the analog color intensity of each pixel. For example:

(0.7V, 0V, 0V) represents a red pixel.
(0.7V, 0.7V, 0V) represents a yellow pixel.

A voltage of 0.7V indicates the maximum intensity for a color, while 0V represents the minimum intensity.

Synchronization Signals:

hsync: Indicates the end of a horizontal line (active area) and prepares the display for the next line.
vsync: Marks the end of the entire visible frame, prompting the display to start a new frame.

The timing diagram on the right illustrates the basic VGA signal structure: The yellow area represents the active display region. The green and orange areas show the front porch and sync intervals.

Why Use a Front and Back Porch?

These timing intervals originate from old CRT displays. The back porch allowed the electron beam to return to the screen's starting position, while the front porch provided a black reference and time to disable the color signals, ensuring no unwanted image artifacts appeared during beam retrace. VGA Signal Generation Since VGA uses analog data transmission for colors, high-speed digital-to-analog converters (DACs) are typically required for high color depth. However, for this experimental design, the FPGA’s digital pins will directly generate color signals. While this approach reduces the number of available colors, it also simplifies the design. Similarly, the vsync and hsync signals will be generated using the FPGA’s digital outputs, enabling proper synchronization by marking the end of each horizontal and vertical display area.

VHDL Design

The implemented controller entity, shown on the right side, features four inputs and three outputs.

Inputs:

CLK_i: The clock input, which must match the actual pixel clock of the desired resolution. For example, for an 800x600@60Hz resolution, the pixel clock must be 40 MHz.
RST_i: A reset signal that resets the core synchronously with the clock.
En_i: An enable signal that starts the operation of the timing generator.
Sync_i: A synchronization input used to synchronize the timing generator.

Outputs:

Active_o: Indicates whether the current pixel is within the active video area.
H_sync_o: Provides the horizontal synchronization signal.
V_sync_o: Provides the vertical synchronization signal.

The design primarily revolves around two counters, responsible for generating horizontal and vertical timing signals. These counters are internally represented by the following signals:

Key Features and Operation:

Reset: The counters can be reset either by the Sync_i signal or the RST_i signal.
Enable Signal: The counters start counting only when the En_i signal is high.

        
          SIGNAL h_sync_int_s : INTEGER := 0;
          SIGNAL v_sync_int_s : INTEGER := 0;

Operation:

The horizontal counter begins counting from 0 and increments until it reaches the end of the line. Once it completes a line, the vertical counter increments by one.
During this process, the current counter values are checked against predefined boundaries:

If the pixel is outside the visible area, the Active_o output is set to low./li>
When the counters are within the horizontal or vertical sync periods, the corresponding H_sync_o or V_sync_o outputs are driven

This structured approach ensures accurate synchronization signals for a VGA display and manages the active video area effectively.

Parametrization:

The core is designed for a fixed output frequency, which can be configured using generic parameters. The key parameters are listed below:

      
        GENERIC

        (

          -- VGA timing definitions in pixels

          h_visible_area : INTEGER := 800;    -- Number of visible horizontal pixels
          h_frontporch   : INTEGER := 40;     -- Horizontal front porch width
          h_sync_pulse   : INTEGER := 128;    -- Horizontal sync pulse width
          h_back_porch   : INTEGER := 88;     -- Horizontal back porch width
          h_whole_line   : INTEGER := 1056;   -- Total horizontal pixels

          v_visible_area : INTEGER := 600;    -- Number of visible vertical lines
          v_frontporch   : INTEGER := 1;      -- Vertical front porch height
          v_sync_pulse   : INTEGER := 4;      -- Vertical sync pulse height
          v_back_porch   : INTEGER := 23;     -- Vertical back porch height
          v_whole_line   : INTEGER := 628     -- Total vertical lines
        );

Using these generic parameters, the core generates appropriate timing signals for the VGA display. The source code for this module can be found on Github .

Testbench:

To create a fully integrable design and verify its functionality, a testbench was developed. This testbench, along with its Makefile for GHDL, is also available on Github . The testbench simulates four images and calculates the timings for each signal transition. This ensures the generation of valid VGA timing signals. The key parameters for the testbench are defined as constants:

      
        CONSTANT half_clock_period_c : TIME := 12.5 ns;   -- Half of the pixel clock period
        CONSTANT clock_period_c : TIME := 2 * half_clock_period_c;

        -- Pixel definitions for the image
        CONSTANT h_visible_area_c : INTEGER := 800;
        CONSTANT h_frontporch_c   : INTEGER := 40;
        CONSTANT h_sync_pulse_c   : INTEGER := 128;
        CONSTANT h_back_porch_c   : INTEGER := 88;
        CONSTANT h_whole_line_c   : INTEGER := 1056;

        CONSTANT v_visible_area_c : INTEGER := 600;
        CONSTANT v_frontporch_c   : INTEGER := 1;
        CONSTANT v_sync_pulse_c   : INTEGER := 4;
        CONSTANT v_back_porch_c   : INTEGER := 23;
        CONSTANT v_whole_line_c   : INTEGER := 628;

Here:

half_clock_period_c represents half of the pixel clock period.
The remaining constants define the pixel timing parameters for the image.

This setup validates the critical timing information required for a compliant VGA signal.